Wow,...
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| Author | Content |
|---|---|
| JaseP May 05, 2011 8:20 AM EDT |
Wow,... This could potentially push back bumping into the end of Moore's Law by 10, 15, maybe even 20 years or more... Couple this with that new mem-RAM & better battery or fuel cell tech, 3D displays & we could start seeing some truly amazing mobile devices inside of 5 years... |
| hkwint May 05, 2011 10:21 AM EDT |
But this tech won't enable more transistors per area though. |
| gus3 May 05, 2011 11:20 AM EDT |
Hans, care to elaborate? (Dumb it down a little; I never took an EE class.) |
| skelband May 05, 2011 12:56 PM EDT |
Maybe it will, maybe it won't. I would imagine that one of the limitations on further shrinkage is the stability of the gate as size diminishes. If I have read correctly, gate leakage in the off state becomes a severe problem once you reach a certain size of conventional gate. Therefore, a smaller 3d transistor with the better performing gate would match the overall performance of a larger 2d transistor. I guess it depends on what you want. Either a lower power, better performing gate, or the same performance on a smaller gate, or some shade in between. I'm sure that heat dissipation is also a factor though I am no expert on these things.... :D |
| JaseP May 05, 2011 1:07 PM EDT |
Potentially, it CAN lead to more transistors per area. One of
things restricting going to smaller die sizes is that all the excess current during idle increases heat. Reduced power could translate to less heat. I suppose it could also generate less interference from neighboring logic circuits, another bar to going to smaller die sizes. They are planing on using these transistors with a 22nm process. The theoretical limits are somewhere between 5nm & 1.5 nm. This new design helps with the electron flow problem. So, instead of tapping out at 10nm, it may be possible to go to 8nm or less. |
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